The present invention is related to the testing and debugging of electronic systems, and, in particular, to on-chip circuits for the test and diagnosis of problems in an integrated circuit.
Heretofore, logic analyzer probes have often been used in the testing and debugging of electronic systems. The logic analyzer probes were coupled to the external pins of components of a digital system in order to capture the sequence of signals after a predefined event (or time stamp) occurs. The captured signals can then be examined to verify correct system behavior or, alternatively, to identify the time and the nature of erroneous behavior in the system.
Furthermore, in the designs of large electronic systems, separate consoles, or service processors, have often been incorporated into the circuit boards of the system. These separate processors have a number of useful functions, including the control of scan strings in the system; the origination of diagnostic signal probes to run on the system, and so forth. The service processors also have diagnostic and scan debug features, including access to the internal registers and memory within the system. The service processors have also been used to bring-up the main system during its power up phase. All of these functions have been useful to system designers for the design, test and debugging of electronic systems.
On the other hand, more and more digital systems, or parts of digital systems, are being integrated in a single component. The resulting complexity and lack of observability of an integrated circuit poses serious problems for the test, debug and bring-up stages of the integrated circuit (IC). For example, observation at the IC component pins of the behavior of an IC system is increasingly difficult. The IC component pins may be very far (in terms of logic hierarchy) from the actual points of interest. The extremely high frequency of digital IC operations and the frequency filtering effects of the large capacitance of the external logic analyzer probes, often prevents a logic analyzer from capturing signals reliably and precisely. There is always an uncertainty regarding the accuracy of signals captured by an external logic analyzer compared to the actual signals values within the IC.
To address the problems of the testing of integrated circuits, special features are being included in many IC designs. For example, one standard technique is xe2x80x9cscanxe2x80x9d whereby, certain internal flip-flops, which are connected to various selected points of the IC, are also connected to form a serial shift register when the IC is configured in a test mode. Straightforward serial shift (i.e.,. scan) operations are utilized to load the flip-flops with desired values, or to read out their present values reflective of the logic states of the selective IC points. Such ICs require special features to reset the flip-flops (i.e., bring the IC to a known starting state). However, the size of integrated circuits has grown to the point where it has become inefficient and expensive to test and debug ICs using solely conventional scan techniques.
Furthermore, variations of the serial scan technique include the use of so-called xe2x80x9cshadow registers.xe2x80x9d IC internal signal states are captured in a duplicate copy, i.e., the shadow register, of certain internal registers. The shadow registers are interconnected by a dedicated internal scan chain. A predetermined event can trigger a snapshot of the internal state values in the shadow registers and the dedicated scan chain shifts the captured signal state without affecting the system operation of the IC. However, this approach has several deficiencies. First, only a single snapshot can be captured and shifted out with each trigger event. This greatly hampers debugging the IC since there is not much visibility of the system activity around a point of interest identified by the trigger event. Secondly, the snapshots can be taken only of those signals in registers which have a shadow register counterpart. Since a shadow register effectively doubles the circuitry for the register, this approach is very costly to implement on a large scale in the IC.
Another test and debug design for ICs is found in a standard, the IEEE 1149.1 Test Access Port and Boundary-Scan Architecture, which prescribes a test controller which responds to a set of predetermined instructions and an instruction register which holds the present instruction which the controller executes. Each instruction is first loaded into the instruction register from a source outside the IC and then that instruction is executed by the controller. While having some advantages of versatility and speed, the standard still binds test and debug procedures to the world external to the IC and thus, limits its performance.
The present invention recognizes that while the advances in IC technology have helped to create the problems of testing and debugging an IC, the advances also point the way toward solving these problems. In accordance with the present invention, special on-chip circuits are used to observe the internal workings of an IC. These circuits operate at internal IC clock rates so that the limitations of the frequency of signals at the IC input and output (I/O) boundary are avoided. Many more points in the IC system are accessed than is feasible with conventional external test and debug processors. Thus the present invention offers advantages which exceed the straight-forward savings in chip space due to miniaturization. Additionally, the present invention reduces the amount of test logic which might have been required elsewhere on the chip.
The present invention also permits the coupling of probes to internal IC points. The points may be selected from a larger number of internal points that may be observed with an external logic analyzer. Besides the greater observability of the internal operations of the IC, the present invention also improves the accuracy of the observations, as compared to an external logic analyzer.
To achieve these ends, the present invention provides for an integrated circuit logic blocks, a control unit, a memory associated with the control unit and a plurality of scan lines. The memory holds instructions for the control unit to perform test and debug operations of the logic blocks. The scan lines are responsive to the control unit for loading test signals for the logic blocks and retrieving test signal results from the logic blocks. The test signals and the test signal results are stored in the memory so that the loading and retrieving operations are performed at one or more clock signal rates internal to the integrated circuit. The integrated circuit also has a plurality of probe lines which are responsive to the control unit for carrying system operation signals at predetermined probe points of the logic blocks. The system operation signals are also stored in the memory so that the system operation signals are retrieved at one or more clock signal rates internal to the integrated circuit.
The present invention also provides for an integrated circuit which has an interface for coupling to an external diagnostic processor, a unit responsive to instructions from the external diagnostics processor, a plurality of probe lines coupled to the unit, and a memory coupled to the unit and to the interface. In response to the unit, the probe lines carry sequential of sets of system operation signals at predetermined probe points of the integrated circuit and the system operation signals are stored in the memory at one or more clock signal rates internal to the integrated circuit. The system operation signals are retrieved from the memory through the interface to the external diagnostic processor at one or more clock signal rates external to the integrated circuit. This allows the external diagnostics processor to process the captured system operation signals.
The present invention further provides for a method of operating an integrated circuit which has logic blocks, a control unit, a memory and a plurality of scan lines of the logic blocks. The memory is loaded with test signals and instructions for the control unit and the scan lines responsive to the control unit are loaded with the test signals for the logic blocks at one or more clock signal rates internal to the integrated circuit. The logic blocks are then operated at one or more clock signal rates internal to the integrated circuit and the resulting test signal results are retrieved from the logic blocks along the scan lines at one or more clock signal rates internal to the integrated circuit. The test signal results are stored in the memory at one or more clock signal rates internal to the integrated circuit; and the stored test results signals are processed in the control unit responsive to the stored instructions in the memory to perform test and debug operations of the logic blocks.